Trench silicide (TS) to gate (PC) (TS-PC) shorts are some of the most common and detrimental failure mechanisms in MOSFET device manufacturing, particularly in the 7 nm technology node and beyond. A known approach for forming a MOSFET device consumes approximately 10 nm of the SiN gate caps during the gate stack reactive-ion etching (RIE) process and then approximately 5 nm more during the removal of the contact etch stop layer (CESL) from small canyon TS structures, as depicted in FIGS. 1A through 1C. The CESL needs to be removed from small canyon TS structures for contact resistance (Rhoc) reduction. However, the resulting gate cap loss can lead to TS-PC or source/drain (CA) to PC (CA-PC) shorts.
FIGS. 1A through 1C schematically illustrate cross-sectional views of the known MOSFET formation process flow. Adverting to FIG. 1A, two laterally separated metal gates 101 are formed over and perpendicular to a fin 103 of the MOSFET device. Each metal gate 101 has sidewall spacers 105 and a SiN gate cap 107, e.g., a self-aligned contact (SAC) cap. A conformal SiN CESL 109 is formed on the bottom and side surfaces of the trench 111 formed between opposing spacers 105 between the metal gates 101, and the trench 111 is filled with an oxide 113. The oxide 113 is then removed, e.g., by RIE, which causes approximately 10 nm of the SiN caps 107 to also be removed, as depicted in FIG. 1B. Adverting to FIG. 1C, when the SiN CESL 109 is subsequently removed, e.g., by RIE, an additional 5 nm of the SiN gate caps 107 is lost because there is no selectivity between the SiN gate caps 107 and the SiN CESL 109. Consequently, TS-PC or CA-PC shorts may occur.
A need therefore exists for methodology for protecting MOSFET nitride gate caps during patterning of small canyon TS structures and the resulting device.